Floating Tap DFE

B. Zhang et al., "A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 50, no. 12, pp. 3089-3100, Dec. 2015.

BroadCom SerDes Design.  Mention OIF CEI-25G standards.  Include a floating tap DFE and a description on why there are restrictions on which tap, floating taps can be applied to.

Receiver includes, CTLE, VGA, 14 tap DFE (8 floating). 
Transmitter, 5 tap FFE

40 dB channels

• "A quarter-rate 14-tap analog DFE including six fixed taps and eight floating taps further equalizes the channel loss and near-end reflection without enhancing channel noise and crosstalk."
• "Because of the quarter-rate topology, the each floating tap selection is limited to every four symbol interval to ease implementation, e.g., Tap7 only selected from symbol 7, 11, 15 and 19, Tap8 only selected from symbol 8, 12, 16 and 20, etc. As wavelength of 25 Gb/s on package/board trace around 0.6 cm, floating taps 7–26 can compensate TX reflection up to 8.5 cm (3.3 inch) length trace."
• I love it how they are able to take a DFE architecture and turn it into a physical specification of how long of a trace they are able to effectively compensate reflections for.