Disclaimer: I've only read up to and including section III but that includes the PAM4 design, which I am interested in at the time.
Great, well written paper. This is written by a university group so I felt like they shared a lot of useful information and were not trying to hide details like it feel like if the group was industry based.
- They have a great (first order) explanation as to when you want to choose PAM4 over NRZ.
- The concept is, the PAM4 eye is 1/3 smaller than the NRZ eye. db(1/3) = -9.5. For 56 Gbps, the Nyquist for NRZ is 28 GHz and 14 GHz for PAM4. Therefore, if the difference in Insertion loss between 28 and 14 G is less than 9.5 dB, you should do NRZ, but if it is larger then PAM4 is a viable option.
- PAM4 Transmitter
- "the number of FFE taps is usually limited to 4 in order to minimize the parasitics".
- May need DLLs to neutralize skews between the multiple data stream, due to the use of clock multiplexing (a half rate clock, quarter rate clock, etc).
- skew may be an interesting impairment to model. This would be a form of DCD
- Summer with tuneable weighting combiner to adjust the level spacing.
- These are needed to compensate for a non-linear optical impairment.
- We could model this behavior in a MATLAB function block but would only be useful if we also had a EML (electroabsortion-modulated) laser block that would create the impairment that the tunable weights would be compensating for.
- Unless an AMI model injected this EML laser impairment, I see little point in including a summer with tunable weights in an AMI model.
- Transmitter includes peaking inductor to increase the edge rate of the transitions.
- PAM4 Receiver
- A pure linear CDR. They say that it naturally handles multiple levels and is some ways easier to implement than a bang-bang CDR.
- Preamp/Equalizer
- They do slightly equalize the signal differently depending on if it goes to the middle (0 Volt threshold) slicer or the upper/lower slicers..
- PAM4 slicers, linear CDR and DFE
- 3 slicers at the 3 PAM4 threshold values
- Linear CDR
- Apply DFE separately to the three slicers
- Question. Why is the DFE after the slicer? I guess I usually combine the slicer with symbol decoder. Here these functions are separated. This allows for a soft decision (slicers, or a 2 bit ADC), followed by some DSP (through the DFE) and finally the PAM4 decoder and retimers make the bit decisions.
- This type of circuit is possible since they have a high precision linear CDR. Then they can operate on the data samples with high confidence.
