Jitter Decomposition by Convolutional Neural Networks

N. Ren, Z. Fu, D. Zhou, H. Liu, Z. Wu and S. Tian, "Jitter Decomposition by Convolutional Neural Networks," in IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 5, pp. 1550-1561, Oct. 2021, doi: 10.1109/TEMC.2020.3047080.

• Jitter decomposition algorithms fall into two categories
• "The first evaluates the error performance of the system, decomposing jitter into DJ and RJ, and estimates total jitter (TJ).
• They present an extensive list including the 2020 paper by G. Soliman that I really liked.
• These methods appear to only have access to the total bathtub.
• "The second category of the jitter decomposition algorithm separates various jitter components from TJ, such as DCD, PJ, ISI, and RJ, to investigate system characteristics and diagnose possible problems in the system.
• These methods appear to have access to the time domain waveform
• It isn't clear in my head the distinction between the two types.
• Summary of their work: "In this article, a novel jitter decomposition by convolutional neural networks (CNNs) is proposed. Its training sample is a jitter histogram obtained by using an advanced design system (ADS) to simulate a high-speed serial link, in which the values of RJ and DJ are adjusted at the transmitter and the jitter histograms are obtained at the receiver. The proposed CNN method has a five-layer convolutional network and a two-layer fully connected layer, which can achieve DJ and RJ decomposition. The same network can also achieve TJ prediction. The jitter histogram pixel image is the input of CNN and the regression RJ, DJ, and TJ values are output of CNN.
• So they setup a bunch of cases where they injected a know amount of RJ and Dual-Dirac DJ into the system and observed the bathtub.
• Should I include Dual-Dirac DJ as an option in my stimulus block? If I do, make it hidden because it would only before science projects . . .
• They input a 2D image of the bathtub and output RJ, DJ and TJ
• Data rate is 1-5 Gb/s!  This is really strange that they would use such slow speeds . . . maybe because jitter is most important for NRZ but SNR is more important for PAM4.
• I stopped reading half way through.  I'm not super impressed with anything based on dual-dirac.  It might be a fun learning to try and reproduce these results but they seem like a lot of work to just get Dj and Rj out of a distribution.  I also question the utility of such analysis as the channel changes and the data rate changes.
• If I ever reproduce these results, I bet changing the channel would break the CNN. This might be interesting to try.  My assumption is that they used a single channel for all of their analysis and changing the channel would totally change the results.

timing mismatch in interleaved ADCs

B. Razavi, "Problem of timing mismatch in interleaved ADCs," Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012, pp. 1-8

• "In addition to raising the conversion speed, interleaving also reduces the metastability rate. Since each channel is given a longer time for conversion, the probability of metastability drops exponentially"
• "The performance of interleaved ADCs is ultimately limited by mismatches among the channels. Gain, offset, and timing mismatches heavily impact the overall signal-to-(noise + distortion) ratio (SNDR) [1] at resolutions of 8 bits or higher. As explained below, the timing mismatch is the most difficult to calibrate because it does not easily lend itself to detection or correction."

224 Gbps

M. Hossain and W. T. Beyene, "Toward 224-Gb/s Electrical Signaling—Modulation, Equalization, and Channel Options," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 11, no. 3, pp. 451-461, March 2021

• Fabulous introduction, they summarized the issues perfectly and mention "constructive use of ISI [5, 11]" which sounds very interesting.
• ceramic vs organic material packages.  Ceramic can have dramatically lower loss packages and reduce reflections from vias but organic packages (most common today) can be much larger.
• "The ceramic substrate shows a loss of about −3 dB, and the organic package loss exceeds −14 dB at frequency of 56 GHz. The ceramic substrate has the advantage of minimizing via reflection, while organic substrate, to support bigger package size, requires a larger core via that increases reflection"
• "Although for simplicity ADCs are often modeled as an effective number of bits (ENOBs), it does not appropriately reflect link performance."
• " Currently, up to 35–37-dB loss compensation is demonstrated in the literature based on ADC-DSP-based solutions." , I assume that they are discussing 112G links. They should have really had a reference here.
• CNRZ suffers from skew issues but CNRZ+ADC is great since the skew isn't a big deal. Any gain mismatch can be easily compensated for in the ADC. 
• "Based on the simulation results, multiwire encoding can compensate up to 40 dB of channel loss and with aggressive FEC and equalization, it can be further extended to 45 dB."
• "multiwire encoding performs significantly better when implemented in digital domain and capable of compensating up to 45 dBs of loss. Obviously, this performance improvement comes at the cost of increased power consumption. Specifically, we need 6 ADCs to decode 5 bits, compared with PAM-4 that requires only one ADC per pair of wire but with higher resolution. One important limitation for multiwire encoding is the spectrum inefficiency compared with PAM-4. Given that we can only send 5 bits over six wires compared with 6 bits over six wires in PAM-4, we need to increase data rate by 20%"
• Discrete Multitone (DMT) Modulation
• Mentioned that this is an option but is not backwards compatable.

Papers to read: 

[5] A. K. M. D. Hossain, Aurangozeb, M. Mohammad and M. Hossain, "A 35 mW 10 Gb/s ADC-DSP less direct digital sequence detector and equalizer in 65 nm CMOS", Proc. IEEE Symp. VLSI Circuits (VLSI-Circuits), pp. 1-2, Jun. 2016.

[11]  W. T. Beyene and A. Amirkhany, "Controlled intersymbol interference design techniques of conventional interconnect systems for data rates beyond 20 Gbps", IEEE Trans. Adv. Packag., vol. 31, no. 4, pp. 731-740, Nov. 2008.

[DMT] B. Nowrouzian, Luqing Wang and W. Agha, "An overview of discrete multitone modulation/demodulation systems in xDSL applications," Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256), Pacific Grove, CA, USA, 2001, pp. 31-35 vol.1

Signal integrity in reflection-limited channels, 2008

 J. F. Buckwalter, "Signal integrity in reflection-limited channels," 2008 IEEE MTT-S International Microwave Symposium Digest, Atlanta, GA, USA, 2008, pp. 1565-1568, doi: 10.1109/MWSYM.2008.4633081.

• This paper analyzes multiple reflections where the channel is a lossy transmission line and the source and load impedance are the main sources of impedance discontinuity.  The paper aims to find an analytic way of quantifying the total ISI. 
• "This work aims to find worst case bounds on the ISI and DDJ caused by reflections" They handle attenuation as a simple factor.
• Did not finish reading paper.  The focus seems to be on finding some simplified equations to estimate the jitter and noise from a simplified channel model.  Interesting but I don't think it is useful to me at this time.

Electrical interconnect potential and limits

B. Casper, "Electrical interconnect potential and limits," 2014 Optical Interconnects Conference, San Diego, CA, USA, 2014, pp. 110-112

• "For system implementations with a fixed power or thermal density budget, power may be the dominant constraint to maximizing bandwidth
• Interesting observation about reported electrical link power consumption vs. optical link power consumption: 
• "A notable aspect of published electrical interconnect energy efficiency calculations is that almost all quotes include the entire power required to transmit and receive data to and from the processor or SoC and tend to include the entire clocking, biases, clock recovery, control, output stage, equalizers, amplifiers, self-test logic, etc. In contrast, many published optical energy efficiencies only include a subset of the overall power required to operate a full link, in some cases only including the output modulation power. 
• "Even with the inclusion of all necessary building blocks, electrical links have demonstrated the ability to achieve better than 1pJ/bit for meter level cable distances"

SI/PI-Database of PCB-Based Interconnects for Machine Learning Applications

 M. Schierholz et al., "SI/PI-Database of PCB-Based Interconnects for Machine Learning Applications," in IEEE Access, vol. 9, pp. 34423-34432, 2021

• A repository of data! What a magnanimous thing to do!
• "Overall 78,961 variations of interconnects are presented. By making this database available we invite other researchers to apply and customize their ML techniques using our results. This provides the possibility to accelerate ML research in EMC engineering without the need to generate expensive data
• "However, [Machine Learning techniques] cannot be easily applied to EMC engineering problems and an adaption to the specific requirements of SI and PI is usually needed [26]–[29]. Mostly this is due to the complex electromagnetic behavior that SI, PI, and EMC problems show, and the difficulty to categorize and describe their three dimensional nature consisting of a wide variety of different components and structures.

Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging

M. Swaminathan, H. M. Torun, H. Yu, J. A. Hejase and W. D. Becker, "Demystifying Machine Learning for Signal and Power Integrity Problems in Packaging," in IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 8, pp. 1276-1295, Aug. 2020

• use CNN: convolutional neural network to model frequency responses.
• "NNs are generally overconfident models, meaning that they assume that the predictions they make are always correct. As expected, this can be dangerous. A better approach is to quantify the error in the predictions
• "The CEL uses the Hilbert transform to relate the real and imaginary parts of the S-parameters, whereas the PEL ensures that the singular values of the S-parameters are less than 1 [26], both derived from the domain knowledge on behavior of passive structures. The key to this NN architecture is the feedback loop shown in Fig. 14, where the weights are automatically adjusted as part of the learning process to ensure that the constraints are satisfied while simultaneously minimizing the error in the response.
• CEL = Causality enforcement layer
• PEL= passivity enforcement layer
• H. M. Torun, A. C. Durgun, K. Aygun and M. Swaminathan, "Enforcing causality and passivity of neural network models of broadband S-parameters", Proc. IEEE 28th Conf. Electr. Perform. Electron. Packag. Syst. (EPEPS), pp. 1-3, Oct. 2019.
• Used 550 S-parameters generated from HFSS to train a package PTH model.  Looks pretty nice.
• "A problem with BO is that it does not scale well as the dimensionality increases. In the SI and PI domain, this occurs when all the parameters have both independent and joint effect (coupling) on f (x), which causes the GP surrogate model to require lots more data to identify these effects
• BO= Bayesian optimization
• GP=Gaussian Process
• They address this issue with their proposed method
• "As mentioned earlier, deterministic NNs covered in Section II assume that the predictions made are always accurate. This can be dangerous since uncertainty of the predictions is as important as the predictions themselves and should be accounted for in the model. We call this as uncertainty quantified model development, which is the subject of this section
• I really like this point they keep making.
• " we introduce the concept of simultaneous model building and optimization. Here, the goal is to jointly derive an accurate predictive model over whole sample space while converging to the worst case scenario. 
• "To prioritize finding the worst case scenario due to its importance in SI and PI problems, we introduce a technique called dropout, as shown in Fig. 30
• 
  
  
  
• The example I was waiting for "IV.C Problem 8 - High speed channel signaling"
• Great example of using adaptive sampling to train a Gaussian Process model that predicts the eye height and width.

BER vs. SNR plot

 M. N. Sakib and O. Liboiron-Ladouceur, "A Study of Error Correction Codes for PAM Signals in Data Center Applications," in IEEE Photonics Technology Letters, vol. 25, no. 23, pp. 2274-2277, Dec.1, 2013

• "Using Monte-Carlo and semi-analytical simulations the signal to noise ratio (SNR) requirement of PAM-N is obtained
• The paper is really about exploring the FEC coding gain of optical systems, it would be very interesting to reproduce these results.

Notes from Jitter Methodology OIF-CEI

https://www.oiforum.com/wp-content/uploads/2019/01/OIF-CEI-04.0.pdf

• Method A: interfaces with no Tx or Rx equalization required for an open eye
• CID (Consecutive Identical Digits) jitter tolerance test pattern
• specify a very specific data pattern that tries to "exercise possible weakness in rise and fall time symmetry"
• [72 zeros + 10328 bits from PRBS31 + 72 ones + 10328 bits from PRBS31]
• Regular JTOL test pattern is PRBS31
• Eye Measurements on compliance channel
• "The opening of the eye shall be calculated using Statistical Eye Analysis methods, as per Annex 2.C.5, and confirmed to be within the requirements at the required BER of the Implementation Agreement, usually,
• "Amplitude at the zero time offset sampling point
• "Time jitter measured at the zero amplitude sampling point
• The trouble is, the "offset sampling point" is not defined in section 2.1.2 or Annex 2.C.5, so hopefully it is defined by the standard that references this? Or maybe it is up to the user to specify the 'best' location. This ambiguity may be due to this section is just used to specify the channel compliance and not the system compliance.
• "A sampling point as defined by the reference receiver shall be used" 
• Where is the reference receiver defined?
• See 2.B.9.1 Annex - Receiver Sample Point
• Transmitter Compliance
• Ensure output jitter is within specified limits
• Measure total wander and relative wander
• Receiver Compliance
• Measure BER to be better than specified for a stressed input signal.

• Method B: interfaces where Tx EQ may be used but Rx EQ not required for an open eye at the BER of interest
• Test Pattern: JTOL and Tx output jitter tests use PRBS31
• Channel Compliance the same as method A
• Transmitter Compliance
• Similar to method A but accounts for the inevitable issue of the Tx EQ alone is unable to open the eye.
• Receiver Compliance nearly the same as method A but requires Rx high probability jitter and gaussian jitter injected.
• Method C: interfaces where Tx EQ may be used and requires Rx CTLE EQ for an open eye at a BER level
• channel compliance the same as methods A and B
• Transmitter Compliance seems to be the same as method B
• Receiver Compliance seems very similar to method B but can include crosstalk and other jitter sources.
• Method D: interfaces where Tx EQ may be used and requires DFE EQ for an open eye
•  The compliance sections seem very very similar to method C.
• Method E: interfaces where "simple Rx EQ may be used to improve the margin of the link" for an open eye and "transparent applications may be used"
• What is a "transparent application"????
• Defines a CID jitter tolerance pattern (same as method A).
• Channel compliance
• Same as the others but "Any parameters that have degrees of freedom e.g. filter coefficients, shall be optimised against the amplitude, at the zero phase offset, as generated by the Statistical Eye Output. e.g. by sweeping all degrees of freedom and selecting the parameters giving the maximum amplitude."
• I wonder if this is an accommodation for COM?
• Transmitter Compliance
• discusses "transparent applications" maybe these are repeater units which transparently transfer along any jitter?
• Receiver Compliance
• "transparent application" use the SJ mask for the specific optical standard.
• Carefully calibrate the injected jitter.
• 2.A Annex - Masks
• Total Wander Masks / Relative Wander Masks
• "Total wander specifications should be considered as accumulated low frequency jitter"
• For JTOL testing, wander is considered a SJ source.
• Random Jitter Mask
• specifies a high frequency random jitter spectrum to use to stress CDR.
• 2.B Annex - Pulse Response Channel Modeling
• Generating a pulse response - how to go from frequency to time domain.
• Basic Pulse Response Definitions
• Definition of the cursor location of pulse. Initially they say this location is at the "maximum signal energy" and then later they say the "exact position of c_0 is arbitrary and is defined specifically by the various methodologies."
• Transmitter Pulse Definition
• Nice description of how to calculate how many dB of emphasis a transmitter has.
• Receiver Pulse Response
• This section seems incomplete, it says "the receiver pulse cursors are then defined as follows" but then only provides a figure without explanation.  I think they punted on this one.
• Time Continuous Transverse Filter
• FFE, FIR, Comb structure or Transverse Filter
• Time Continuous Zero-Pole Equalizer adaptation
• CTE with 3 poles and 3 zeros (not sure how this is stable) they use the "Nelder-Mead Multidimensional Unconstrained Non-Linear Minimization Method" to figure out the filter.  Would like more details here, sounds interesting.
• 2.B.9.1 Annex - Receiver Sample Point
• "A receiver shall be allowed to either position the centre sampling point fully independently to the signal transitions or exactly in between the mean crossover of the receiver signal.
• The above is the whole section and is the first definitive description of how to center the clock. 
• 2.C Annex - Jitter Modeling
• Disparages dual Dirac jitter model and instead encourages the "stateye" approach
• "Jitter is defined as the deviation of the signal transition from an origin, usually its mean.
• High Frequency jitter vs. Wander
• Jitter below the CDR bandwidth is wander, jitter above the CDR bandwidth is high frequency jitter.
• Total vs. Relative Wander
• Great description of how to generate SJ with two slightly different frequencies as they beat against each other they generate different types of jitter.  Very helpful.
• The measurements in 2.E.2 and 2.E.3 help as it shows that total wander is measured against an external reference clock and relative wander is measured against an extracted clock.
• Jitter distributions
• "The low probability part of the jitter distribution can be described by two components"
• Unbounded Gaussian distribution function
• Bounded Gaussian distribution function
• "this conversion from BER to Q [using the standard equation] is only valid given a large time offset from the optimal sampling point. . . Any accurate prediction of the BER towards the centre of the eye should be done using Marcum's Q function , and is outside the scope of this document"
• What is Marcum's Q function? https://en.wikipedia.org/wiki/Marcum_Q-function
• Annex - Statistical Eye Methodology
• Great discussion of statistical eye calculation
• 2.D Annex - Definition of CEI Test Patterns
• PRBS31 - uses taps 28 and 31, which unfortunately is not what my prbs.m function uses.
• SSPR - short stress pattern random
• designed to have a baseline wander and timing content that is as stressful as 10,000 years of random binary.  This is sounds like a version of importance sampling.
• uses PRBS28 with taps 25 and 28 with CID (Consecutive Identical Digits) segments interspersed.
• SSPS-16, short stress pattern SDH 16
• "STM-16 framed random binary" so this must be specific to some standard
• This pattern is PRBS28 + CID + various preamble frame patterns.
• SSPS-64: short stress pattern SDH-64 frame
• Hex patterns provided for
• SSPR, SSPS-16, SSPS-64
• 2.E Appendix - Lab Setups
• Define a Golden PLL as "have at maximum a bandwidth of baud rate over 1667, with a maximum of 20dB/dec rolloff, until at least baud rate over 16.67, with no peaking around the corner frequency.
• "The High Probability and Gaussian Jitter components should be extracted from the bathtub measurement using the methodology defined in Annex 2.C.4.6.
• Annex 2.C.4.6 looks very much like dual Dirac method, I wonder what the differences (if any) are.
• Discuss some jitter decomposition methods
• Total Transmit Wander Measurement
• "The peak to peak total wander of the extracted clock should be measured using a scope trigger by the reference clock. The measured peak to peak wander should be verified to be bounded by repeating the measurement for ever increasing periods of time until the measurement is constant.
• Relative Transmit Wander Measurement
• "The peak to peak relative wander between the extracted clocks should be measured using a scope trigger by one of the extracted clocks. The measured peak to peak wander should be verified to be bounded by repeating the measurement for ever increasing periods of time until the measurement is constant.
• Jitter Tolerance
• JTOL test includes injecting total and relative SJ as well as other jitter sources.
• Jitter Transfer Function
• "The peak to peak jitter for a 60 second period measured on the scope should be compared before and after the application of the sinusoidal jitter. The ratio of the difference to the jitter applied is then defined as the jitter transfer function.
• 2.F Appendix - BER Adjustment Methodology
• Extrapolation of correlated bounded Gaussian jitter to low BERs
• If possible use combined spectral and oscilloscope methods to estimate jitter flavors
• methods for determining error of BER estimation

 

Magic: Literature Search

• R. Mateosian, "Manuals and guest reviews [Micro review]," in IEEE Micro, vol. 13, no. 3, pp. 84-87, June 1993.  REVIEW, High-Speed Digital Design - A Handbook of Black Magic
• "This book aims to alleviate a problem in the education of digital designers. Over the last couple of decades, the analog circuit principles that apply to high-speed digital design have fallen out of standard college curricula-for the simple reason that they are largely irrelevant at the speeds most designers have been working with. Now, however, as speeds increase, designers lack the training to deal with the “black magic” of managing high-speed effects"
• Shaughnessy, Andy. "Howard W. Johnson: The wizard of black magic. (People to Know)." Printed Circuit Design, vol. 18, no. 4, Apr. 2001, p. 34+. 
• [could not access article, sent request]
• H. Boss, "Demystifying Signal and Power Integrity [From the Guest Editor's Desk]," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 6-10, Aug. 2011
• This is an editors comments on the rest of the IEEE microwave magazine articles.
• The definition of "High Speed" changes every year
• history, Analog circuits --> digital circuits --> realization that digital circuits have real analog effects.  mix signal application (digital and analog)
• H. Johnson, "High-Speed Digital Design," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 42-50, Aug. 2011
• second paragraph (emphasis is mine): "For example, most digital engineers are not equipped either by training or natural inclination to comprehend the intricacies of traveling-wave physics [2]. They may learn necessary bits and pieces of this theory through on-the-job training, but rarely attain the full level of physical understanding common among professionals in the microwave industry.
• E. Bogatin, "Essential Principles of Signal Integrity," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 34-41, Aug. 2011
• This is the entire conclusion (emphasis is mine): "High-speed digital design is driven by the analog effects of interconnects. These are fundamentally driven by the overlap of Maxwell’s equations and board design. While simulations can help optimize a design, it is still fundamentally an engineer’s design intuition that establishes the starting place. The earlier in the design process problems can be identified and designed out, the shorter the development time, the lower the development cost, and the greater the chance of an acceptable design on the first pass. The stronger your signal integrity design intuition, the more effective you will be in this era of high-speed products. 
• "Wizard of Meno Park" --> Edison, people ascribe to magic that which they don't understand
• I think that part of the mystery is that so many disciplines must be applied to solve a signal integrity problem, electromagnetics, statistics, signal processing, etc.
• Moore's law, more bandwidth compounds the issue, increasing frequencies and shrinking structures, moves us from the 
• wavelength of signal vs. feature size of structure -- <where is the nice illustrationin Furse's bio book?>
• H. W. Johnson. (1998, Mar. 2). Why digital engineers don’t believe in EMC. EMC Soc. Newslett. [Online]. Available: www.sigcon.com/Pubs/news/noEMC.htm 
• Nice article

ADC - Sam Palermo - IEEE Microwave Magazine 2019

S. Kiran, S. Cai, Y. Zhu, S. Hoyos and S. Palermo, "Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processing in Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers," in IEEE Microwave Magazine, vol. 20, no. 5, pp. 62-79, May 2019

• "This article presents on overview of ADC-based serial link receivers and a discussion of two important roles played by the DSP: ADC calibration and digital equalization
• Calls the two types of receivers 'mixed-signal' or what I would call analog serdes and 'ADC-based' receiver
• "While the difficult design of robust analog delay elements typically limits the number of FFE taps in mixed-signal receivers, it is straightforward to implement high tap-count digital FFEs in the DSP of ADC-based receivers.
• "A key challenge in mixed-signal DFE design is achieving sufficient linearity to subtract the multilevel ISI encountered in PAM-4 systems. Another major difficulty faced in both mixed-signal and digital implementations is meeting the critical timing associated with feeding back the previous symbol decisions.
• They reference three ways to determine the DFE tap values 1) least-mean-squares algorithm (1985), 2) an eye-opening monitor-based approach (2007) or 3) transition detector-based method (2006).
• ADC quantization noise
• Under certain conditions, which are generally met by ADCs with the uniformly spaced quantization levels commonly used in these systems, this deterministic quantization error can be treated as an additive, uniformly distributed, independent noise term [ref 1996].
• quantization noise is amplified by the digital FFE
• A question that an architect will want answer is how many ADC bits do I need.  This number increases with the loss of the interconnect and is limited by quantization noise.  15 dB channel only needs 3 bits and 35 dB channel needs 6 bits (in their example). Modulation format also influences the number of ADC bits needed.
• Typical PAM-4 systems have 7- to 8-b resolution and have around 5- to 6-b ENOB (effective number of bits) at Nyquist.
• PAM-2 systems are usually 5- to 6-b resolution and have 5- to 4.5-b ENOB.
• ADC topologies
• Flash ADC: fast conversion by employing a bank of 2^R comparators, with their thresholds set to every quantification threshold.  This is fast but power and space hungry when R is large.  Typically have 6-b resolution or less.
• Binary/multibit search ADC: combine the advantages of flash and SAR ADC. Use a binary search algorithm.  Has power savings like SAR ADC but still has the same space footprint as Flash ADC.
• SAR ADC: "a binary search process over several clock cycles, where a comparison is made with a reference value stored on a reference digital-to-analog converter (DAC) to determine whether the sampled signal is above or below the reference value at each cycle. The comparison result is used to update the reference value to move it closer to the input value in predetermined step sizes. Since a binary decision is made at each step, only a single comparator is necessary. 
• 
  
  
  
  
• How to speed up the SAR ADC
• Asynchronous SAR that "uses a ready signal generated locally at the end conversion step to trigger the next conversion, eliminating the need for a global high-frequency synchronous clock"
• multibit conversion "where more than one bit is resolved at the same time by using multiple DACs to generate reference voltages that are moved closer to the input voltage.
• "use a dedicated comparator for each conversion step to simplify the feedback logic and remove the latch precharge delay"
• Uniform vs non-uniform quantization ADC.  Nonuniform-quantization ADCs can be implemented with threshold levels set to optimize the achievable BER and not to optimize the ENOB as traditional uniform-quantization 
• Time-interleaving
• mismatch  results in ENOB and BER degradation.
• gain errors, 5% typical
• bandwidth errors, 5% typical
• skew errors, 850 fs
• offset errors, 10 mv offset
• They show some interesting output frequency spectrum plots when these errors are introduced.
• Discuss calibration techniques
• "Given that the digital equalizer is often designed in a parallel form, with the number of parallel paths matching or being an integer multiple of the number of ADC channels, each parallel equalizer will always see the same order of samples from a particular group of unit ADCs. If the parallel equalizers are independently adapted, then the differences in the  equalizer coefficients can be used to detect unit ADC mismatch and guide the correction circuitry, or the parallel equalizers can simply have independent coefficients to equalize their respective input channels, which include the unit ADC mismatches.
• There are techniques to model the time-interleaved ADC as a linear, periodically time-variant system.  This is done with pulse responses! [S. Kiran et al., "Modeling of ADC-based serial link receivers with embedded and digital equalization", IEEE Trans. Compon. Packag. Manuf. Technol.]
• Digital Equalization
• FFE: 
• "FFEs render themselves very suitable for digital implementations for several reasons. First, they can be effectively pipelined and implemented in a parallel form (Figure 16), leading to relaxed timing requirements. Second, the relaxed timing critical paths can be exploited through power supply scaling to improve power efficiency. Third, the FFE architecture is modulation format-independent, supporting both the common PAM-2 and PAM-4 modulation schemes.
• "However, because these linear equalizers are often set to simply invert the channel response, frequencies where notches are present in the channel can result in large gain peaks in the FFE response and significant amplification of noise and crosstalk.
• "while FFEs are effective at canceling ISI in well-behaved channels with smooth loss profiles, their performance is not as effective in channels with spectral notches resulting from reflections due to connectors and via stubs.
• DFE:
• "offer the significant advantage of canceling postcursor ISI without noise and crosstalk amplification.
• "implementations are difficult because of the challenging feedback-timing path
• "methods that can significantly lessen the critical path delay are loop unrolling and look-ahead multiplexing.
• loop unrolling with N-tap DFE 
• PAM-2: number of slicers = 2^N
• PAM-4: number of slicers = 4^N
• look-ahead multiplexing
• DSP resolution
• "ensure that the BER is not significantly impacted by round-off errors.
• RJA: The metric used to investigate trade-offs seems to be Voltage margin at a BER of 1e-6.  This is a useful insight into how I should quantify performance of my example
• " Verification of ADC and DSP functionality is also aided by observing the predecision histograms present in the DSP, as shown in Figure 25 with four distinct concentrations resulting from a PAM-4 input signal.

Power Optimized ADC-Based Serial Link Receiver - Chen 2012

E. Chen, R. Yousry and C. K. Yang, "Power Optimized ADC-Based Serial Link Receiver," in IEEE Journal of Solid-State Circuits, vol. 47, no. 4, pp. 938-951, April 2012

One of the readings from Sam Palermo's course

• The main issue with ADC receivers is their power consumption, thus the focus of many of the papers is on how the power is reduced.
• Primary benefit of ADC is that it enables the benefits of DSP. 
• The trade-off they explored is how much pre-filtering (CTLE and FIR before the ADC) to use as opposed to doing it all in DSP.  Doing some equalization in the AFE can save 1-2 bits in required ADC resolution.
• Only read up to section III

Maxim SAR ADC Tutorial

 https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1080.html

UNDERSTANDING SAR ADCS: THEIR ARCHITECTURE AND COMPARISON WITH OTHER ADCS

• Successive-approximation-register (SAR) analog-to-digital converters (ADC)
• "SAR ADC basically implements a binary search algorithm
• 
  
  
  
• "Although there are many variations for implementing a SAR ADC, the basic architecture is quite simple (see Figure 1). The analog input voltage (VIN) is held on a track/hold. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to 1). This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided to the ADC. A comparison is then performed to determine if VIN is less than, or greater than, VDAC. If VIN is greater than VDAC, the comparator output is a logic high, or 1, and the MSB of the N-bit register remains at 1. Conversely, if VIN is less than VDAC, the comparator output is a logic low and the MSB of the register is cleared to logic 0. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete and the N-bit digital word is available in the register.
• "Generally speaking, an N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete."
• "another notable feature of SAR ADCs: power dissipation scales with the sample rate. . . . This scaled power dissipation is especially useful in low-power applications or applications where the data acquisition is not continuous
• "A SAR ADC's speed is limited by: (1) The settling time of the DAC, which must settle to within the resolution of the overall converter, for example, ½ LSB (2) The comparator, which must resolve small differences in VIN and VDAC within the specified time and (3) The logic overhead
• "the linearity of the overall ADC is limited by the linearity of the DAC"
• "Many SAR ADCs use a capacitive DAC that provides an inherent track/hold function. A capacitive DAC consists of an array of N capacitors with binary weighted values plus one "dummy LSB" capacitor.
• "Calibration is usually initiated by the user or done automatically on power-up. To reduce the effects of noise, each calibration experiment is performed many times (about 14,000 clock cycles in the MAX195), and the results are averaged.
• Other ADC Architectures
• Pipelined ADCs
• "A pipelined ADC employs a parallel structure in which each stage works on 1 to a few bits (of successive samples) concurrently.
• Flash ADCs
• "A flash ADC is comprised of a large bank of comparators, each consisting of wideband, low-gain preamp(s) followed by a latch. 
• "The primary trade-off between a flash ADC's speed is the SAR ADC's significantly lower power consumption and smaller form factor.
• Sigma-Delta Converters
• "Sigma-delta converters trade speed for resolution. The need to sample many times (at least 16 times and often more) to produce one final sample dictates that the internal analog components in the sigma-delta modulator operate much faster than the final data rate.

Multidrop Transmission System Based on Reflection-Canceling Scheme With Reflection Compensation Lines

 Y. Akeboshi, H. Itakura and C. Miyazaki, "Multidrop Transmission System Based on Reflection-Canceling Scheme With Reflection Compensation Lines," in IEEE Transactions on Electromagnetic Compatibility, vol. 62, no. 6, pp. 2576-2584, Dec. 2020

"reflection-canceling scheme that can be applied to the bus-type multidrop transmission system

"Two RCLs (reflection compensation line) are added to both ends of the main bus line to intentionally cause reflection waves

"there exists a possibility of canceling the reflection waves with opposite polarity through the adequate design of the reflection coefficient of each segment.

"Since the RCL uses a reflection cancelation strategy, the application of the method is constrained to a multidrop system consisting of line segments with equivalent lengths. This situation is quite common in the high-speed digital transmission of backplane systems or DDR SDRAM wiring, although it is technically challenging in order to keep signal integrity within the required specification.

RJA: Very cool idea.  They applied it here to loss-less transmission lines but the general idea is sound.  I would be interested to apply my ripple analysis to this same problem and see how it works here. What order of CSLT would be necessary? Could this formulation be used to optimize the system?

RJA: They also introduced to me "Evolutionary gradient search" EGS that is used to avoid local minimums of a typical gradient search approach.  Very nice.