Clock and Data Recovery

 Lee, Hae-Chang. An estimation approach to clock and data recovery. Diss. Stanford University, 2007.

• Section 2.1.1 Linear Phase Detector, gives a great overview of the Hogge phase detector, how it works (Creates two pulses that cancel each other out when zero phase difference), why it was popular (linear PD are easy to analyze), it's downsides (if the CDR is digital you need to convert output from analog to digital).

• KPD (loop gain) is define as the slope of the transfer function at 0.

• Section 2.2, Benefits of digital loop filter
• "Additional benefits of this architecture deriving from the digital loop filter are reduced pattern dependent jitter caused by leakage currents in the loop filter in the presence of CID, reduced phase offset error caused by charge pump current mismatch, reduced sensitivity to supply noise, and finally loop dynamics that are not affected by process, voltage and temperature variations."
• Section 2.2.1 Bang-Bang Phase Detector
• "KPD (loop gain) is difficult to define as the slope of the curve through the zero crossing is infinite (Figure 2.8 (b)). A method to approximate KPD exists and will be explored in a later section.
• Section 4.3.2 Jitter Tolerance
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• Also swept reference offset as part of the JTOL testing of the CDR
• "The first order CDR can only take corrective action after the error has occurred. For this reason, a time lag exists between the TX data transitions and the recovered clock in steady state which in turn offsets the data sampling point from its optimum.
• "The second order CDR learns the phase offset ramp rate (frequency offset) from past bits and takes predictive correction on the deterministic phase offset trajectory. This allows the second order CDR to drive the average steady state phase estimation error to zero.
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Memristors and Artificial Intelligence

From March 2023 IEEE Spectrum: https://spectrum.ieee.org/memristor-devices-ai

• "Memristors, or memory resistors, are essentially switches that can remember which electric state they were toggled to after their power is turned off."
• "They can be used to both compute and store data"
• This allows for a better neuron emulation and in tests yielded excellent power consumption per computation of multiply operations.
• Understanding how to simulate this type of circuit before fabrication is likely a hot future topic.
• What is impressive is the new design and manufacturing of these circuits.  Prior efforts had poor yields and reliability but the new ones have had yields of 100%.  This is from a team in Israel.
• The devices could withstand 100,000 cycles of programming and could retain data for more than 10 years.
• I wonder if the limitation is the 100,000 cycles of programming and erasing.  Isn't every signal that goes through programming and erasing? If a clock cycle is 1 ns and we assume that each memristor was utilized 1/10th of the time, then the entire circuit would only last 1 second! (1ns * 100,000 * 1/0.1).  I wonder how they will address this deficiency.
• Regardless this is way cool
• The next researches from France use memristors for Bayesian reasoning. They also used knowledge-based neural nets (KBNN) to solve recognition of handwriting tasks.
• "Bayesian reasoning is often thought of as computationally expensive with conventional electronics"  -- but the new work was able to perform the handwriting recognition with 1/800 to 1/5000 the energy.