Magic: Literature Search

• R. Mateosian, "Manuals and guest reviews [Micro review]," in IEEE Micro, vol. 13, no. 3, pp. 84-87, June 1993.  REVIEW, High-Speed Digital Design - A Handbook of Black Magic
• "This book aims to alleviate a problem in the education of digital designers. Over the last couple of decades, the analog circuit principles that apply to high-speed digital design have fallen out of standard college curricula-for the simple reason that they are largely irrelevant at the speeds most designers have been working with. Now, however, as speeds increase, designers lack the training to deal with the “black magic” of managing high-speed effects"
• Shaughnessy, Andy. "Howard W. Johnson: The wizard of black magic. (People to Know)." Printed Circuit Design, vol. 18, no. 4, Apr. 2001, p. 34+. 
• [could not access article, sent request]
• H. Boss, "Demystifying Signal and Power Integrity [From the Guest Editor's Desk]," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 6-10, Aug. 2011
• This is an editors comments on the rest of the IEEE microwave magazine articles.
• The definition of "High Speed" changes every year
• history, Analog circuits --> digital circuits --> realization that digital circuits have real analog effects.  mix signal application (digital and analog)
• H. Johnson, "High-Speed Digital Design," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 42-50, Aug. 2011
• second paragraph (emphasis is mine): "For example, most digital engineers are not equipped either by training or natural inclination to comprehend the intricacies of traveling-wave physics [2]. They may learn necessary bits and pieces of this theory through on-the-job training, but rarely attain the full level of physical understanding common among professionals in the microwave industry.
• E. Bogatin, "Essential Principles of Signal Integrity," in IEEE Microwave Magazine, vol. 12, no. 5, pp. 34-41, Aug. 2011
• This is the entire conclusion (emphasis is mine): "High-speed digital design is driven by the analog effects of interconnects. These are fundamentally driven by the overlap of Maxwell’s equations and board design. While simulations can help optimize a design, it is still fundamentally an engineer’s design intuition that establishes the starting place. The earlier in the design process problems can be identified and designed out, the shorter the development time, the lower the development cost, and the greater the chance of an acceptable design on the first pass. The stronger your signal integrity design intuition, the more effective you will be in this era of high-speed products. 
• "Wizard of Meno Park" --> Edison, people ascribe to magic that which they don't understand
• I think that part of the mystery is that so many disciplines must be applied to solve a signal integrity problem, electromagnetics, statistics, signal processing, etc.
• Moore's law, more bandwidth compounds the issue, increasing frequencies and shrinking structures, moves us from the 
• wavelength of signal vs. feature size of structure -- <where is the nice illustrationin Furse's bio book?>
• H. W. Johnson. (1998, Mar. 2). Why digital engineers don’t believe in EMC. EMC Soc. Newslett. [Online]. Available: www.sigcon.com/Pubs/news/noEMC.htm 
• Nice article

ADC - Sam Palermo - IEEE Microwave Magazine 2019

S. Kiran, S. Cai, Y. Zhu, S. Hoyos and S. Palermo, "Digital Equalization With ADC-Based Receivers: Two Important Roles Played by Digital Signal Processing in Designing Analog-to-Digital-Converter-Based Wireline Communication Receivers," in IEEE Microwave Magazine, vol. 20, no. 5, pp. 62-79, May 2019

• "This article presents on overview of ADC-based serial link receivers and a discussion of two important roles played by the DSP: ADC calibration and digital equalization
• Calls the two types of receivers 'mixed-signal' or what I would call analog serdes and 'ADC-based' receiver
• "While the difficult design of robust analog delay elements typically limits the number of FFE taps in mixed-signal receivers, it is straightforward to implement high tap-count digital FFEs in the DSP of ADC-based receivers.
• "A key challenge in mixed-signal DFE design is achieving sufficient linearity to subtract the multilevel ISI encountered in PAM-4 systems. Another major difficulty faced in both mixed-signal and digital implementations is meeting the critical timing associated with feeding back the previous symbol decisions.
• They reference three ways to determine the DFE tap values 1) least-mean-squares algorithm (1985), 2) an eye-opening monitor-based approach (2007) or 3) transition detector-based method (2006).
• ADC quantization noise
• Under certain conditions, which are generally met by ADCs with the uniformly spaced quantization levels commonly used in these systems, this deterministic quantization error can be treated as an additive, uniformly distributed, independent noise term [ref 1996].
• quantization noise is amplified by the digital FFE
• A question that an architect will want answer is how many ADC bits do I need.  This number increases with the loss of the interconnect and is limited by quantization noise.  15 dB channel only needs 3 bits and 35 dB channel needs 6 bits (in their example). Modulation format also influences the number of ADC bits needed.
• Typical PAM-4 systems have 7- to 8-b resolution and have around 5- to 6-b ENOB (effective number of bits) at Nyquist.
• PAM-2 systems are usually 5- to 6-b resolution and have 5- to 4.5-b ENOB.
• ADC topologies
• Flash ADC: fast conversion by employing a bank of 2^R comparators, with their thresholds set to every quantification threshold.  This is fast but power and space hungry when R is large.  Typically have 6-b resolution or less.
• Binary/multibit search ADC: combine the advantages of flash and SAR ADC. Use a binary search algorithm.  Has power savings like SAR ADC but still has the same space footprint as Flash ADC.
• SAR ADC: "a binary search process over several clock cycles, where a comparison is made with a reference value stored on a reference digital-to-analog converter (DAC) to determine whether the sampled signal is above or below the reference value at each cycle. The comparison result is used to update the reference value to move it closer to the input value in predetermined step sizes. Since a binary decision is made at each step, only a single comparator is necessary. 
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• How to speed up the SAR ADC
• Asynchronous SAR that "uses a ready signal generated locally at the end conversion step to trigger the next conversion, eliminating the need for a global high-frequency synchronous clock"
• multibit conversion "where more than one bit is resolved at the same time by using multiple DACs to generate reference voltages that are moved closer to the input voltage.
• "use a dedicated comparator for each conversion step to simplify the feedback logic and remove the latch precharge delay"
• Uniform vs non-uniform quantization ADC.  Nonuniform-quantization ADCs can be implemented with threshold levels set to optimize the achievable BER and not to optimize the ENOB as traditional uniform-quantization 
• Time-interleaving
• mismatch  results in ENOB and BER degradation.
• gain errors, 5% typical
• bandwidth errors, 5% typical
• skew errors, 850 fs
• offset errors, 10 mv offset
• They show some interesting output frequency spectrum plots when these errors are introduced.
• Discuss calibration techniques
• "Given that the digital equalizer is often designed in a parallel form, with the number of parallel paths matching or being an integer multiple of the number of ADC channels, each parallel equalizer will always see the same order of samples from a particular group of unit ADCs. If the parallel equalizers are independently adapted, then the differences in the  equalizer coefficients can be used to detect unit ADC mismatch and guide the correction circuitry, or the parallel equalizers can simply have independent coefficients to equalize their respective input channels, which include the unit ADC mismatches.
• There are techniques to model the time-interleaved ADC as a linear, periodically time-variant system.  This is done with pulse responses! [S. Kiran et al., "Modeling of ADC-based serial link receivers with embedded and digital equalization", IEEE Trans. Compon. Packag. Manuf. Technol.]
• Digital Equalization
• FFE: 
• "FFEs render themselves very suitable for digital implementations for several reasons. First, they can be effectively pipelined and implemented in a parallel form (Figure 16), leading to relaxed timing requirements. Second, the relaxed timing critical paths can be exploited through power supply scaling to improve power efficiency. Third, the FFE architecture is modulation format-independent, supporting both the common PAM-2 and PAM-4 modulation schemes.
• "However, because these linear equalizers are often set to simply invert the channel response, frequencies where notches are present in the channel can result in large gain peaks in the FFE response and significant amplification of noise and crosstalk.
• "while FFEs are effective at canceling ISI in well-behaved channels with smooth loss profiles, their performance is not as effective in channels with spectral notches resulting from reflections due to connectors and via stubs.
• DFE:
• "offer the significant advantage of canceling postcursor ISI without noise and crosstalk amplification.
• "implementations are difficult because of the challenging feedback-timing path
• "methods that can significantly lessen the critical path delay are loop unrolling and look-ahead multiplexing.
• loop unrolling with N-tap DFE 
• PAM-2: number of slicers = 2^N
• PAM-4: number of slicers = 4^N
• look-ahead multiplexing
• DSP resolution
• "ensure that the BER is not significantly impacted by round-off errors.
• RJA: The metric used to investigate trade-offs seems to be Voltage margin at a BER of 1e-6.  This is a useful insight into how I should quantify performance of my example
• " Verification of ADC and DSP functionality is also aided by observing the predecision histograms present in the DSP, as shown in Figure 25 with four distinct concentrations resulting from a PAM-4 input signal.

Power Optimized ADC-Based Serial Link Receiver - Chen 2012

E. Chen, R. Yousry and C. K. Yang, "Power Optimized ADC-Based Serial Link Receiver," in IEEE Journal of Solid-State Circuits, vol. 47, no. 4, pp. 938-951, April 2012

One of the readings from Sam Palermo's course

• The main issue with ADC receivers is their power consumption, thus the focus of many of the papers is on how the power is reduced.
• Primary benefit of ADC is that it enables the benefits of DSP. 
• The trade-off they explored is how much pre-filtering (CTLE and FIR before the ADC) to use as opposed to doing it all in DSP.  Doing some equalization in the AFE can save 1-2 bits in required ADC resolution.
• Only read up to section III

Maxim SAR ADC Tutorial

 https://www.maximintegrated.com/en/design/technical-documents/tutorials/1/1080.html

UNDERSTANDING SAR ADCS: THEIR ARCHITECTURE AND COMPARISON WITH OTHER ADCS

• Successive-approximation-register (SAR) analog-to-digital converters (ADC)
• "SAR ADC basically implements a binary search algorithm
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• "Although there are many variations for implementing a SAR ADC, the basic architecture is quite simple (see Figure 1). The analog input voltage (VIN) is held on a track/hold. To implement the binary search algorithm, the N-bit register is first set to midscale (that is, 100... .00, where the MSB is set to 1). This forces the DAC output (VDAC) to be VREF/2, where VREF is the reference voltage provided to the ADC. A comparison is then performed to determine if VIN is less than, or greater than, VDAC. If VIN is greater than VDAC, the comparator output is a logic high, or 1, and the MSB of the N-bit register remains at 1. Conversely, if VIN is less than VDAC, the comparator output is a logic low and the MSB of the register is cleared to logic 0. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is complete and the N-bit digital word is available in the register.
• "Generally speaking, an N-bit SAR ADC will require N comparison periods and will not be ready for the next conversion until the current one is complete."
• "another notable feature of SAR ADCs: power dissipation scales with the sample rate. . . . This scaled power dissipation is especially useful in low-power applications or applications where the data acquisition is not continuous
• "A SAR ADC's speed is limited by: (1) The settling time of the DAC, which must settle to within the resolution of the overall converter, for example, ½ LSB (2) The comparator, which must resolve small differences in VIN and VDAC within the specified time and (3) The logic overhead
• "the linearity of the overall ADC is limited by the linearity of the DAC"
• "Many SAR ADCs use a capacitive DAC that provides an inherent track/hold function. A capacitive DAC consists of an array of N capacitors with binary weighted values plus one "dummy LSB" capacitor.
• "Calibration is usually initiated by the user or done automatically on power-up. To reduce the effects of noise, each calibration experiment is performed many times (about 14,000 clock cycles in the MAX195), and the results are averaged.
• Other ADC Architectures
• Pipelined ADCs
• "A pipelined ADC employs a parallel structure in which each stage works on 1 to a few bits (of successive samples) concurrently.
• Flash ADCs
• "A flash ADC is comprised of a large bank of comparators, each consisting of wideband, low-gain preamp(s) followed by a latch. 
• "The primary trade-off between a flash ADC's speed is the SAR ADC's significantly lower power consumption and smaller form factor.
• Sigma-Delta Converters
• "Sigma-delta converters trade speed for resolution. The need to sample many times (at least 16 times and often more) to produce one final sample dictates that the internal analog components in the sigma-delta modulator operate much faster than the final data rate.

Multidrop Transmission System Based on Reflection-Canceling Scheme With Reflection Compensation Lines

 Y. Akeboshi, H. Itakura and C. Miyazaki, "Multidrop Transmission System Based on Reflection-Canceling Scheme With Reflection Compensation Lines," in IEEE Transactions on Electromagnetic Compatibility, vol. 62, no. 6, pp. 2576-2584, Dec. 2020

"reflection-canceling scheme that can be applied to the bus-type multidrop transmission system

"Two RCLs (reflection compensation line) are added to both ends of the main bus line to intentionally cause reflection waves

"there exists a possibility of canceling the reflection waves with opposite polarity through the adequate design of the reflection coefficient of each segment.

"Since the RCL uses a reflection cancelation strategy, the application of the method is constrained to a multidrop system consisting of line segments with equivalent lengths. This situation is quite common in the high-speed digital transmission of backplane systems or DDR SDRAM wiring, although it is technically challenging in order to keep signal integrity within the required specification.

RJA: Very cool idea.  They applied it here to loss-less transmission lines but the general idea is sound.  I would be interested to apply my ripple analysis to this same problem and see how it works here. What order of CSLT would be necessary? Could this formulation be used to optimize the system?

RJA: They also introduced to me "Evolutionary gradient search" EGS that is used to avoid local minimums of a typical gradient search approach.  Very nice.