A. Viveros-Wacher, R. Baca-Baylón, F. E. Rangel-Patiño, J. L. Silva-Cortés, E. A. Vega-Ochoa and J. E. Rayas-Sánchez, "Fast Jitter Tolerance Testing for High-Speed Serial Links in Post-Silicon Validation," in IEEE Transactions on Electromagnetic Compatibility, vol. 64, no. 2, pp. 516-523, April 2022, doi: 10.1109/TEMC.2021.3122348.
Jitter Tolerance (JTOL) tests take a long time to run in the lab as evidenced by this table from the paper:
- ME: JTOL testing is a Bit error rate (BER) test while sweeping sinusoidal jitter amplitude and frequency.
- XAUI, PCIe, USB and SATA all have slightly different JTOL tests
- "In this article, we present a novel approach to dramatically accelerate JTOL testing based on a modified golden section direct search optimization algorithm."
- "To perform a JTOL test, each protocol specification defines a calibration procedure prior to the JTOL execution. This procedure defines the specific random jitter (JR), bounded uncorrelated jitter (JBU), duty-cycle distortion, and ISI values injected to the test pattern, which remain constant throughout the JTOL test, while JP (jitter periodic) is varied in both amplitude and frequency."
- These guys use JTOL to validate the system, in SerDes Toolbox we would want to use JTOL to characterize the CDR during design. But regardless, both are desired.
- "In the traditional way to run JTOL testing, at each frequency point, the value of JP is initialized at a sufficiently low starting point to guarantee a PASS result from the BERT. Then, JP is increased by a certain amount, typically equivalent to the minimum value allowed by the BERT equipment for best accuracy. Then, a test is performed at the compliance BER. This is iteratively done until the BERT yields a FAIL. The result reported at each frequency point is the last JP value that yields a PASS.
- For a given frequency their algorithm adjusts SJ amplitude until the desired BER is achieved.
- Overall an interesting idea to consider.